1. Field of the Invention
The present invention relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2009-291848, filed Dec. 24, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, semiconductor devices having a multi-layered wiring structure have been manufactured. Such a semiconductor device has a structure such that wires are provided on a surface of each layer, and contact plugs electrically connects wires on different layers. The wires are formed with high density, thereby making manufacturing processes complicated.
FIG. 1 illustrates a general method of manufacturing a semiconductor wafer 2, on which a semiconductor device having a multi-layered wiring structure of a related art. The semiconductor wafer 2 includes a dicing region C, which defines a region including a chip region A and a fuse element formation region B.
Firstly, semiconductor elements, such as a MOS transistor 201a and a capacitor 201d, are formed on a silicon substrate 200. Then, a single-or-multi-layered inter-layer insulating film 201b is formed over the semiconductor elements. Thus, an element layer 201 is formed. As long as the above conditions are satisfied and a fuse element for remedying defective chips is included in the wiring structure, not only a DRAM (Dynamic Random Access Memory), but also a memory element such as SRAM (Static Random Access Memory) and a FLASH memory, a logic circuit, or the like may be formed as the semiconductor wafer 2.
Then, a contact plug 201c is fowled so as to vertically penetrate the inter-layer insulating film 201b in the fuse element formation region B and the dicing region C. The contact plug 201c is made of a conductive material, such as Titanium (Ti) and Tungsten (W). The contact plug 201c connects the MOS transistor 201a and a multi-layered structure 221 (a first wiring structure 210, a second wiring structure 220, and a third wiring structure 230) that will be explained later.
Then, a first silicon nitride film 202 and an inter-layer film 203 are sequentially formed over the chip region A, an upper surface of the contact plug 201c in the fuse element formation region B and the dicing region C, and the uppermost inter-layer insulating film 201b. The inter-layer film 203 includes a first low-k film (low dielectric material film) made of silicon (Si), carbon (C), oxygen (O), or the like.
The reason that the low-k film is formed over the contact plug 201c is to reduce parasitic capacitance and thereby to prevent a delay of a signal through the contact plug 201c. The low-k film is defined in this specification as a film having a lower dielectric constant than that of a pure silicon oxide film. Specifically, the low-k film is defined as a film having a k-value that is smaller than 3.9. Instead of a single-layered low-k film, the inter-layer film 203 may be a multi-layered structure including a low-k film and a thin silicon oxide film over the low-k film. The thin silicon oxide film may be formed by a plasma CVD (Chemical Vapor Deposition) process. The thin silicon oxide film is formed to achieve moisture absorption and to prevent scratching in the CMP process.
Then, a first contact hole 204a, which penetrates the first silicon nitride film 202 and the first inter-layer film 203, is formed. Then, a barrier metal film and a copper film are sequentially formed in this order so as to fill the first contact hole 204a and to cover the inter-layer film 203 including the first low-k film. The barrier metal film is made of Ti, Ta (tantalum), Mn (manganese), or the like. The barrier metal film prevents copper from diffusing into the inter-layer insulating film 201b. Thus, deterioration of elements due to diffusion of copper can be prevented.
Then, the barrier metal film over the first inter-layer film 203 and the copper film over the barrier metal film are polished using a CMP (Chemical Mechanical Polishing) method to form a first wire (Cu wire) 204. Thus, a first wiring structure 210, which includes the first silicon nitride film 202, the first inter-layer film 203, and the first wire 204, is formed. In the fuse element formation region B, the first wire 204 functions as a fuse element. When the first wire 204 is diced by laser irradiation or the like, a predetermined circuit operation can be carried out.
Then, a first diffusion prevention insulating film 205, a second inter-layer insulating film 206, and a second wire 207 are formed in a similar manner as the process of forming the first wiring structure 210. Thus, a second wiring structure 220, which includes the first diffusion prevention insulating film 205, the second inter-layer film 206, and the second wire 207, is formed over the first wiring structure 210.
The first diffusion prevention insulating film 205 is provided to prevent diffusion of copper. The first diffusion prevention insulating film 205 may be made of, for example, a silicon nitride film. Instead, a silicon nitride film containing carbon (C) to reduce the dielectric constant may be used. The first and second wires 204 and 207 are collectively connected to the contact plug using a dual damascene method. However, the dual damascene method is a known method, and therefore an explanation thereof is omitted here.
Then, a second diffusion prevention insulating film 208 and a third inter-layer insulating film 209 are formed over the second wiring structure 220. Then, a third contact hole 211a is formed so as to penetrate the third inter-layer insulating film 209 and to expose the second wire 207.
Then, the third contact hole 211a is filled with Ti and W, or with Al using a reflow sputtering method at a high temperature, to form a plug. The method of forming the plug has little relation to the present invention. Therefore, the detailed explanation thereof is omitted here. A process using the reflow sputtering process is shown in the drawings of the related art and embodiments of the present invention that will be explained later.
Then, a third wire (Al wire) 211, which fills the third contact hole 211a, is formed by a sputtering method or a reflow sputtering method. The third wire 211 is made of Al or the like. The third wire 211 includes a lower portion 211b and an upper portion 211c. The lower portion 211b of the third wire 211 penetrates the third inter-layer insulating film 209 and the second diffusion prevention insulating film 208, and functions as a contact plug. The upper portion 211c extends upwardly from an upper surface of the third inter-layer insulating film 209, and functions as a wiring layer.
The reason that Al is used as the material of the third wire 211 is that Al has a great affinity for a bonding process that will be explained later. Thus, a third wiring structure 230, which includes the second diffusion prevention insulating film 208, the third inter-layer insulating film 209, and the lower portion 211b of the third wire 211, is formed. In this manner, a multi-layered wiring structure 221, which includes the first wiring structure 210, the second wiring structure 220, and the third wiring structure 230, is formed.
Then, a cover insulating film 212 is formed so as to cover the third inter-layer insulating film 209 and the upper portion 211c of the third wire 211. The cover insulating film 212 includes a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a multi-layered film including these films. Then, a polyimide layer 213 is formed so as to cover the cover insulating film 212. The polyimide layer 213 functions as a buffer for the chip.
Thus, a die seal ring 240, which includes the upper portion 211c of the third wire 211, the cover insulating film 212, and the polyimide layer 213, is formed in the dicing region. C. The die seal ring 240 surrounds a periphery of each chip including the chip region A and the fuse element formation region B, and functions as a protection ring. Then, a hole for a bonding pad (not shown) is formed. Thus, a manufacturing pre-process is completed.
As a method of manufacturing a semiconductor device having such a multi-layered wiring structure, PCT international publication No. WO 2004/097917 discloses a method of simultaneously carrying out a process of farming a groove for preventing dicing crack and a process of forming a hole for a pad.
However, the above methods have the following problems. In a manufacturing post-process as shown in FIG. 2, generally, a wafer is diced into multiple chips by using a dicing blade or laser irradiation to the dicing region C. During the dicing process, cracking K occurs on a dicing surface. Then, a different material is deposited on the dicing surface, and the cracking further proceeds between the first inter-layer film 203 and the first diffusion prevention insulating film 205 which have different Young's moduli. If the cracking K further proceeds over the die seal ring portion and reaches the chip region A, the moisture resistance of the semiconductor chip degrades, thereby causing defects of the semiconductor device.
To solve the problem, a method is often used in which a deep crack stop trench (not shown) is formed in the dicing region C around the die seal ring 240 surrounding the chip, in order to divide the boundary surface between the first inter-layer film 203 and the first diffusion prevention insulating film 205.
Regarding the manufacturing method of the related art, in the process of forming a hole for a bonding pad and the bonding pad, the polyimide layer 213 and the cover insulating film 212 in a specific region are etched to expose an upper surface of the upper portion 211c of the third wire 211. At the same time, the second inter-layer insulating film 206 in the fuse element formation region B and the dicing region C is etched so that part of the second inter-layer insulating film 206 remains in the fuse element formation region B.
At this time, it is preferable to simultaneously form a crack stop trench (not shown) and a hole for a bonding pad. This is because the manufacturing process can be simplified by dividing the first inter-layer film 203 in the dicing region C at the same time of forming the hole for the bonding pad.
If the etching process further proceeds after the state of FIG. 1 where the crack stop trench is formed, however, the first wire (fuse element) 204 in the fuse element formation region B is also exposed. For this reason, the moisture resistance of the semiconductor wafer 2 degrades, thereby causing defects of the semiconductor device.
To prevent this, at least the fuse element formation region B and the crack stop trench are processed using different masks. In other words, a process of etching the second inter-layer insulating film 206 in the fuse element formation region B and a process of forming the crack stop trench have to be carried out separately, which causes an increase in the number of processes and an increase in manufacturing costs. For this reason, it has been difficult to simultaneously form the crack stop trench and the hole for the bonding pad without exposing the fuse element (first wire 204).